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You searched for: mediatype:texts AND collection:theides AND subject:"SRAM"
[texts]Analysis and Simulation of Sub-threshold Leakage Current in P3 SRAM Cell at DSM Technology for Multimedia Applications
In this work, the analysis and simulation work is proposed for the low-power (reduced subthreshold leakage) and high performance SRAM bit-cells for mobile multimedia applications in deep-sub-micron (DSM) CMOS technology. The sub-threshold leakage analysis of the P3 SRAM cell has been carried out. It has been observed that due to pMOS stacking and full supply body-biasing, there is a reduction of 70% and 86% in sub-threshold leakage current at VDD=0.8V and VDD=0.7V respectively as compared to con...
Keywords: Sub-threshold Leakage; Standby Power; Stacking; Conventional SRAM cell; PP-SRAM; P3-SRAM
Downloads: 63
[texts]Built-in Self Repair for SRAM Array using Redundancy - A. Padma Sravani, Dr. M. Satyam
In this paper, a built-in self repair technique for word-oriented two-port SRAM memories is presented. The technique is implemented by additional hardware design instead of traditional software diagnostic procedures and the computation time is minimized. A built-in self-test (BIST) is used to detect the faulty locations which are isolated immediately after detection. Therefore, the redirection process can be executed as soon as possible...
Keywords: SRAM; two-port memories; PVT faults; fault isolation; BISR
Downloads: 185
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